Vladimir Kutkovoy
8 months ago
commit
5e820d43ee
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Debug/ |
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settings/ |
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/.vscode |
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;*******************************************************************************
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;* @File Name : startup_stm32g431xx.s
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;* @Author : MCD Application Team
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;* @Brief : STM32G431xx Devices vector
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;*******************************************************************************
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;* Description : This module performs:
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;* - Set the initial SP
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;* - Set the initial PC == _iar_program_start,
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;* - Set the vector table entries with the exceptions ISR
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;* address.
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;* - Branches to main in the C library (which eventually
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;* calls main()).
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;* After Reset the Cortex-M4 processor is in Thread mode,
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;* priority is Privileged, and the Stack is set to Main.
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;********************************************************************************
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;* @attention
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;*
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;* Copyright (c) 2019 STMicroelectronics.
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;* All rights reserved.
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;*
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;* This software is licensed under terms that can be found in the LICENSE file
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;* in the root directory of this software component.
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;* If no LICENSE file comes with this software, it is provided AS-IS.
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;
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;*******************************************************************************
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;
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; The modules in this file are included in the libraries, and may be replaced
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; by any user-defined modules that define the PUBLIC symbol _program_start or
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; a user defined start symbol.
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; To override the cstartup defined in the library, simply add your modified
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; version to the workbench project.
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;
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; The vector table is normally located at address 0.
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; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
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; The name "__vector_table" has special meaning for C-SPY:
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; it is where the SP start value is found, and the NVIC vector
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; table register (VTOR) is initialized to this address if != 0.
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;
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; Cortex-M version
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;
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MODULE ?cstartup |
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;; Forward declaration of sections.
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SECTION CSTACK:DATA:NOROOT(3) |
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SECTION .intvec:CODE:NOROOT(2) |
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EXTERN __iar_program_start |
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EXTERN SystemInit |
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PUBLIC __vector_table |
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DATA |
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__vector_table |
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DCD sfe(CSTACK) |
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD MemManage_Handler ; MPU Fault Handler
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DCD BusFault_Handler ; Bus Fault Handler
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DCD UsageFault_Handler ; Usage Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD DebugMon_Handler ; Debug Monitor Handler
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD WWDG_IRQHandler ; Window WatchDog
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DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
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DCD RTC_TAMP_LSECSS_IRQHandler ; RTC, TAMP and RCC LSE_CSS through the EXTI line
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DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
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DCD FLASH_IRQHandler ; FLASH
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DCD RCC_IRQHandler ; RCC
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DCD EXTI0_IRQHandler ; EXTI Line0
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DCD EXTI1_IRQHandler ; EXTI Line1
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DCD EXTI2_IRQHandler ; EXTI Line2
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DCD EXTI3_IRQHandler ; EXTI Line3
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DCD EXTI4_IRQHandler ; EXTI Line4
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DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
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DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
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DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
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DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
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DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
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DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
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DCD 0 ; Reserved
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DCD ADC1_2_IRQHandler ; ADC1 and ADC2
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DCD USB_HP_IRQHandler ; USB Device High Priority
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DCD USB_LP_IRQHandler ; USB Device Low Priority
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DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
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DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
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DCD EXTI9_5_IRQHandler ; External Line[9:5]s
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DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break, Transition error, Index error and TIM15
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DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
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DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger, Commutation, Direction change, Index and TIM17
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DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
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DCD TIM2_IRQHandler ; TIM2
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DCD TIM3_IRQHandler ; TIM3
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DCD TIM4_IRQHandler ; TIM4
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DCD I2C1_EV_IRQHandler ; I2C1 Event
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DCD I2C1_ER_IRQHandler ; I2C1 Error
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DCD I2C2_EV_IRQHandler ; I2C2 Event
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DCD I2C2_ER_IRQHandler ; I2C2 Error
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DCD SPI1_IRQHandler ; SPI1
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DCD SPI2_IRQHandler ; SPI2
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DCD USART1_IRQHandler ; USART1
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DCD USART2_IRQHandler ; USART2
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DCD USART3_IRQHandler ; USART3
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DCD EXTI15_10_IRQHandler ; External Line[15:10]
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DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
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DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line
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DCD TIM8_BRK_IRQHandler ; TIM8 Break, Transition error and Index error Interrupt
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DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt
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DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger, Commutation, Direction change and Index Interrupt
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DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD LPTIM1_IRQHandler ; LP TIM1 interrupt
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DCD 0 ; Reserved
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DCD SPI3_IRQHandler ; SPI3
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DCD UART4_IRQHandler ; UART4
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DCD 0 ; Reserved
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DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&3 underrun errors
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DCD TIM7_IRQHandler ; TIM7
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DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
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DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
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DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
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DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
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DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD UCPD1_IRQHandler ; UCPD1
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DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3
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DCD COMP4_IRQHandler ; COMP4
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD CRS_IRQHandler ; CRS Interrupt
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DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD FPU_IRQHandler ; FPU
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD RNG_IRQHandler ; RNG global interrupt
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DCD LPUART1_IRQHandler ; LP UART 1 interrupt
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DCD I2C3_EV_IRQHandler ; I2C3 Event
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DCD I2C3_ER_IRQHandler ; I2C3 Error
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DCD DMAMUX_OVR_IRQHandler ; DMAMUX overrun global interrupt
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD CORDIC_IRQHandler ; CORDIC
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DCD FMAC_IRQHandler ; FMAC
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; Default interrupt handlers.
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;;
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THUMB |
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PUBWEAK Reset_Handler |
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SECTION .text:CODE:NOROOT:REORDER(2) |
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Reset_Handler |
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LDR R0, =SystemInit |
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BLX R0 |
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LDR R0, =__iar_program_start |
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BX R0 |
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PUBWEAK NMI_Handler |
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SECTION .text:CODE:NOROOT:REORDER(1) |
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NMI_Handler |
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B NMI_Handler |
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PUBWEAK HardFault_Handler |
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SECTION .text:CODE:NOROOT:REORDER(1) |
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HardFault_Handler |
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B HardFault_Handler |
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PUBWEAK MemManage_Handler |
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SECTION .text:CODE:NOROOT:REORDER(1) |
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MemManage_Handler |
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B MemManage_Handler |
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PUBWEAK BusFault_Handler |
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SECTION .text:CODE:NOROOT:REORDER(1) |
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BusFault_Handler |
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B BusFault_Handler |
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PUBWEAK UsageFault_Handler |
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SECTION .text:CODE:NOROOT:REORDER(1) |
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UsageFault_Handler |
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B UsageFault_Handler |
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PUBWEAK SVC_Handler |
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SECTION .text:CODE:NOROOT:REORDER(1) |
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SVC_Handler |
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B SVC_Handler |
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PUBWEAK DebugMon_Handler |
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SECTION .text:CODE:NOROOT:REORDER(1) |
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DebugMon_Handler |
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B DebugMon_Handler |
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PUBWEAK PendSV_Handler |
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SECTION .text:CODE:NOROOT:REORDER(1) |
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PendSV_Handler |
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B PendSV_Handler |
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PUBWEAK SysTick_Handler |
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SECTION .text:CODE:NOROOT:REORDER(1) |
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SysTick_Handler |
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B SysTick_Handler |
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PUBWEAK WWDG_IRQHandler |
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SECTION .text:CODE:NOROOT:REORDER(1) |
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WWDG_IRQHandler |
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B WWDG_IRQHandler |
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PUBWEAK PVD_PVM_IRQHandler |
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SECTION .text:CODE:NOROOT:REORDER(1) |
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PVD_PVM_IRQHandler |
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B PVD_PVM_IRQHandler |
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PUBWEAK RTC_TAMP_LSECSS_IRQHandler |
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SECTION .text:CODE:NOROOT:REORDER(1) |
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RTC_TAMP_LSECSS_IRQHandler |
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B RTC_TAMP_LSECSS_IRQHandler |
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PUBWEAK RTC_WKUP_IRQHandler |
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SECTION .text:CODE:NOROOT:REORDER(1) |
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RTC_WKUP_IRQHandler |
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B RTC_WKUP_IRQHandler |
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PUBWEAK FLASH_IRQHandler |
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SECTION .text:CODE:NOROOT:REORDER(1) |
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FLASH_IRQHandler |
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B FLASH_IRQHandler |
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PUBWEAK RCC_IRQHandler |
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SECTION .text:CODE:NOROOT:REORDER(1) |
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RCC_IRQHandler |
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B RCC_IRQHandler |
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PUBWEAK EXTI0_IRQHandler |
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SECTION .text:CODE:NOROOT:REORDER(1) |
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EXTI0_IRQHandler |
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B EXTI0_IRQHandler |
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PUBWEAK EXTI1_IRQHandler |
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SECTION .text:CODE:NOROOT:REORDER(1) |
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EXTI1_IRQHandler |
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B EXTI1_IRQHandler |
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PUBWEAK EXTI2_IRQHandler |
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SECTION .text:CODE:NOROOT:REORDER(1) |
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EXTI2_IRQHandler |
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B EXTI2_IRQHandler |
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PUBWEAK EXTI3_IRQHandler |
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SECTION .text:CODE:NOROOT:REORDER(1) |
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EXTI3_IRQHandler |
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B EXTI3_IRQHandler |
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PUBWEAK EXTI4_IRQHandler |
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SECTION .text:CODE:NOROOT:REORDER(1) |
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EXTI4_IRQHandler |
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B EXTI4_IRQHandler |
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PUBWEAK DMA1_Channel1_IRQHandler |
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SECTION .text:CODE:NOROOT:REORDER(1) |
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DMA1_Channel1_IRQHandler |
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B DMA1_Channel1_IRQHandler |
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PUBWEAK DMA1_Channel2_IRQHandler |
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SECTION .text:CODE:NOROOT:REORDER(1) |
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DMA1_Channel2_IRQHandler |
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B DMA1_Channel2_IRQHandler |
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PUBWEAK DMA1_Channel3_IRQHandler |
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SECTION .text:CODE:NOROOT:REORDER(1) |
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DMA1_Channel3_IRQHandler |
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B DMA1_Channel3_IRQHandler |
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PUBWEAK DMA1_Channel4_IRQHandler |
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SECTION .text:CODE:NOROOT:REORDER(1) |
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DMA1_Channel4_IRQHandler |
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B DMA1_Channel4_IRQHandler |
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PUBWEAK DMA1_Channel5_IRQHandler |
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SECTION .text:CODE:NOROOT:REORDER(1) |
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DMA1_Channel5_IRQHandler |
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B DMA1_Channel5_IRQHandler |
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PUBWEAK DMA1_Channel6_IRQHandler |
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SECTION .text:CODE:NOROOT:REORDER(1) |
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DMA1_Channel6_IRQHandler |
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B DMA1_Channel6_IRQHandler |
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PUBWEAK ADC1_2_IRQHandler |
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SECTION .text:CODE:NOROOT:REORDER(1) |
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ADC1_2_IRQHandler |
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B ADC1_2_IRQHandler |
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PUBWEAK USB_HP_IRQHandler |
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SECTION .text:CODE:NOROOT:REORDER(1) |
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USB_HP_IRQHandler |
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B USB_HP_IRQHandler |
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PUBWEAK USB_LP_IRQHandler |
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SECTION .text:CODE:NOROOT:REORDER(1) |
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USB_LP_IRQHandler |
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B USB_LP_IRQHandler |
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PUBWEAK FDCAN1_IT0_IRQHandler |
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SECTION .text:CODE:NOROOT:REORDER(1) |
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FDCAN1_IT0_IRQHandler |
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B FDCAN1_IT0_IRQHandler |
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PUBWEAK FDCAN1_IT1_IRQHandler |
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SECTION .text:CODE:NOROOT:REORDER(1) |
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FDCAN1_IT1_IRQHandler |
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B FDCAN1_IT1_IRQHandler |
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PUBWEAK EXTI9_5_IRQHandler |
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SECTION .text:CODE:NOROOT:REORDER(1) |
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EXTI9_5_IRQHandler |
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B EXTI9_5_IRQHandler |
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PUBWEAK TIM1_BRK_TIM15_IRQHandler |
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SECTION .text:CODE:NOROOT:REORDER(1) |
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TIM1_BRK_TIM15_IRQHandler |
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B TIM1_BRK_TIM15_IRQHandler |
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PUBWEAK TIM1_UP_TIM16_IRQHandler |
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SECTION .text:CODE:NOROOT:REORDER(1) |
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TIM1_UP_TIM16_IRQHandler |
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B TIM1_UP_TIM16_IRQHandler |
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PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler |
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SECTION .text:CODE:NOROOT:REORDER(1) |
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TIM1_TRG_COM_TIM17_IRQHandler |
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B TIM1_TRG_COM_TIM17_IRQHandler |
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PUBWEAK TIM1_CC_IRQHandler |
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SECTION .text:CODE:NOROOT:REORDER(1) |
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TIM1_CC_IRQHandler |
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B TIM1_CC_IRQHandler |
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PUBWEAK TIM2_IRQHandler |
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SECTION .text:CODE:NOROOT:REORDER(1) |
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TIM2_IRQHandler |
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B TIM2_IRQHandler |
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PUBWEAK TIM3_IRQHandler |
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SECTION .text:CODE:NOROOT:REORDER(1) |
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TIM3_IRQHandler |
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B TIM3_IRQHandler |
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PUBWEAK TIM4_IRQHandler |
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SECTION .text:CODE:NOROOT:REORDER(1) |
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TIM4_IRQHandler |
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B TIM4_IRQHandler |
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PUBWEAK I2C1_EV_IRQHandler |
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SECTION .text:CODE:NOROOT:REORDER(1) |
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I2C1_EV_IRQHandler |
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B I2C1_EV_IRQHandler |
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PUBWEAK I2C1_ER_IRQHandler |
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SECTION .text:CODE:NOROOT:REORDER(1) |
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I2C1_ER_IRQHandler |
||||||
|
B I2C1_ER_IRQHandler |
||||||
|
|
||||||
|
PUBWEAK I2C2_EV_IRQHandler |
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1) |
||||||
|
I2C2_EV_IRQHandler |
||||||
|
B I2C2_EV_IRQHandler |
||||||
|
|
||||||
|
PUBWEAK I2C2_ER_IRQHandler |
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1) |
||||||
|
I2C2_ER_IRQHandler |
||||||
|
B I2C2_ER_IRQHandler |
||||||
|
|
||||||
|
PUBWEAK SPI1_IRQHandler |
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1) |
||||||
|
SPI1_IRQHandler |
||||||
|
B SPI1_IRQHandler |
||||||
|
|
||||||
|
PUBWEAK SPI2_IRQHandler |
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1) |
||||||
|
SPI2_IRQHandler |
||||||
|
B SPI2_IRQHandler |
||||||
|
|
||||||
|
PUBWEAK USART1_IRQHandler |
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1) |
||||||
|
USART1_IRQHandler |
||||||
|
B USART1_IRQHandler |
||||||
|
|
||||||
|
PUBWEAK USART2_IRQHandler |
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1) |
||||||
|
USART2_IRQHandler |
||||||
|
B USART2_IRQHandler |
||||||
|
|
||||||
|
PUBWEAK USART3_IRQHandler |
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1) |
||||||
|
USART3_IRQHandler |
||||||
|
B USART3_IRQHandler |
||||||
|
|
||||||
|
PUBWEAK EXTI15_10_IRQHandler |
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1) |
||||||
|
EXTI15_10_IRQHandler |
||||||
|
B EXTI15_10_IRQHandler |
||||||
|
|
||||||
|
PUBWEAK RTC_Alarm_IRQHandler |
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1) |
||||||
|
RTC_Alarm_IRQHandler |
||||||
|
B RTC_Alarm_IRQHandler |
||||||
|
|
||||||
|
PUBWEAK USBWakeUp_IRQHandler |
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1) |
||||||
|
USBWakeUp_IRQHandler |
||||||
|
B USBWakeUp_IRQHandler |
||||||
|
|
||||||
|
PUBWEAK TIM8_BRK_IRQHandler |
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1) |
||||||
|
TIM8_BRK_IRQHandler |
||||||
|
B TIM8_BRK_IRQHandler |
||||||
|
|
||||||
|
PUBWEAK TIM8_UP_IRQHandler |
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1) |
||||||
|
TIM8_UP_IRQHandler |
||||||
|
B TIM8_UP_IRQHandler |
||||||
|
|
||||||
|
PUBWEAK TIM8_TRG_COM_IRQHandler |
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1) |
||||||
|
TIM8_TRG_COM_IRQHandler |
||||||
|
B TIM8_TRG_COM_IRQHandler |
||||||
|
|
||||||
|
PUBWEAK TIM8_CC_IRQHandler |
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1) |
||||||
|
TIM8_CC_IRQHandler |
||||||
|
B TIM8_CC_IRQHandler |
||||||
|
|
||||||
|
PUBWEAK LPTIM1_IRQHandler |
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1) |
||||||
|
LPTIM1_IRQHandler |
||||||
|
B LPTIM1_IRQHandler |
||||||
|
|
||||||
|
PUBWEAK SPI3_IRQHandler |
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1) |
||||||
|
SPI3_IRQHandler |
||||||
|
B SPI3_IRQHandler |
||||||
|
|
||||||
|
PUBWEAK UART4_IRQHandler |
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1) |
||||||
|
UART4_IRQHandler |
||||||
|
B UART4_IRQHandler |
||||||
|
|
||||||
|
PUBWEAK TIM6_DAC_IRQHandler |
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1) |
||||||
|
TIM6_DAC_IRQHandler |
||||||
|
B TIM6_DAC_IRQHandler |
||||||
|
|
||||||
|
PUBWEAK TIM7_IRQHandler |
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1) |
||||||
|
TIM7_IRQHandler |
||||||
|
B TIM7_IRQHandler |
||||||
|
|
||||||
|
PUBWEAK DMA2_Channel1_IRQHandler |
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1) |
||||||
|
DMA2_Channel1_IRQHandler |
||||||
|
B DMA2_Channel1_IRQHandler |
||||||
|
|
||||||
|
PUBWEAK DMA2_Channel2_IRQHandler |
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1) |
||||||
|
DMA2_Channel2_IRQHandler |
||||||
|
B DMA2_Channel2_IRQHandler |
||||||
|
|
||||||
|
PUBWEAK DMA2_Channel3_IRQHandler |
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1) |
||||||
|
DMA2_Channel3_IRQHandler |
||||||
|
B DMA2_Channel3_IRQHandler |
||||||
|
|
||||||
|
PUBWEAK DMA2_Channel4_IRQHandler |
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1) |
||||||
|
DMA2_Channel4_IRQHandler |
||||||
|
B DMA2_Channel4_IRQHandler |
||||||
|
|
||||||
|
PUBWEAK DMA2_Channel5_IRQHandler |
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1) |
||||||
|
DMA2_Channel5_IRQHandler |
||||||
|
B DMA2_Channel5_IRQHandler |
||||||
|
|
||||||
|
PUBWEAK UCPD1_IRQHandler |
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1) |
||||||
|
UCPD1_IRQHandler |
||||||
|
B UCPD1_IRQHandler |
||||||
|
|
||||||
|
PUBWEAK COMP1_2_3_IRQHandler |
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1) |
||||||
|
COMP1_2_3_IRQHandler |
||||||
|
B COMP1_2_3_IRQHandler |
||||||
|
|
||||||
|
PUBWEAK COMP4_IRQHandler |
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1) |
||||||
|
COMP4_IRQHandler |
||||||
|
B COMP4_IRQHandler |
||||||
|
|
||||||
|
PUBWEAK CRS_IRQHandler |
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1) |
||||||
|
CRS_IRQHandler |
||||||
|
B CRS_IRQHandler |
||||||
|
|
||||||
|
PUBWEAK SAI1_IRQHandler |
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1) |
||||||
|
SAI1_IRQHandler |
||||||
|
B SAI1_IRQHandler |
||||||
|
|
||||||
|
PUBWEAK FPU_IRQHandler |
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1) |
||||||
|
FPU_IRQHandler |
||||||
|
B FPU_IRQHandler |
||||||
|
|
||||||
|
PUBWEAK RNG_IRQHandler |
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1) |
||||||
|
RNG_IRQHandler |
||||||
|
B RNG_IRQHandler |
||||||
|
|
||||||
|
PUBWEAK LPUART1_IRQHandler |
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1) |
||||||
|
LPUART1_IRQHandler |
||||||
|
B LPUART1_IRQHandler |
||||||
|
|
||||||
|
PUBWEAK I2C3_EV_IRQHandler |
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1) |
||||||
|
I2C3_EV_IRQHandler |
||||||
|
B I2C3_EV_IRQHandler |
||||||
|
|
||||||
|
PUBWEAK I2C3_ER_IRQHandler |
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1) |
||||||
|
I2C3_ER_IRQHandler |
||||||
|
B I2C3_ER_IRQHandler |
||||||
|
|
||||||
|
PUBWEAK DMAMUX_OVR_IRQHandler |
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1) |
||||||
|
DMAMUX_OVR_IRQHandler |
||||||
|
B DMAMUX_OVR_IRQHandler |
||||||
|
|
||||||
|
PUBWEAK DMA2_Channel6_IRQHandler |
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1) |
||||||
|
DMA2_Channel6_IRQHandler |
||||||
|
B DMA2_Channel6_IRQHandler |
||||||
|
|
||||||
|
PUBWEAK CORDIC_IRQHandler |
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1) |
||||||
|
CORDIC_IRQHandler |
||||||
|
B CORDIC_IRQHandler |
||||||
|
|
||||||
|
PUBWEAK FMAC_IRQHandler |
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1) |
||||||
|
FMAC_IRQHandler |
||||||
|
B FMAC_IRQHandler |
||||||
|
|
||||||
|
END |
||||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,269 @@ |
|||||||
|
/**
|
||||||
|
****************************************************************************** |
||||||
|
* @file stm32g4xx.h |
||||||
|
* @author MCD Application Team |
||||||
|
* @brief CMSIS STM32G4xx Device Peripheral Access Layer Header File. |
||||||
|
* |
||||||
|
* The file is the unique include file that the application programmer |
||||||
|
* is using in the C source code, usually in main.c. This file contains: |
||||||
|
* - Configuration section that allows to select: |
||||||
|
* - The STM32G4xx device used in the target application |
||||||
|
* - To use or not the peripheral’s drivers in application code(i.e. |
||||||
|
* code will be based on direct access to peripheral’s registers |
||||||
|
* rather than drivers API), this option is controlled by |
||||||
|
* "#define USE_HAL_DRIVER" |
||||||
|
* |
||||||
|
****************************************************************************** |
||||||
|
* @attention |
||||||
|
* |
||||||
|
* Copyright (c) 2019 STMicroelectronics. |
||||||
|
* All rights reserved. |
||||||
|
* |
||||||
|
* This software is licensed under terms that can be found in the LICENSE file |
||||||
|
* in the root directory of this software component. |
||||||
|
* If no LICENSE file comes with this software, it is provided AS-IS. |
||||||
|
* |
||||||
|
****************************************************************************** |
||||||
|
*/ |
||||||
|
|
||||||
|
/** @addtogroup CMSIS
|
||||||
|
* @{ |
||||||
|
*/ |
||||||
|
|
||||||
|
/** @addtogroup stm32g4xx
|
||||||
|
* @{ |
||||||
|
*/ |
||||||
|
|
||||||
|
#ifndef __STM32G4xx_H |
||||||
|
#define __STM32G4xx_H |
||||||
|
|
||||||
|
#ifdef __cplusplus |
||||||
|
extern "C" { |
||||||
|
#endif /* __cplusplus */ |
||||||
|
|
||||||
|
/** @addtogroup Library_configuration_section
|
||||||
|
* @{ |
||||||
|
*/ |
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief STM32 Family |
||||||
|
*/ |
||||||
|
#if !defined (STM32G4) |
||||||
|
#define STM32G4 |
||||||
|
#endif /* STM32G4 */ |
||||||
|
|
||||||
|
/* Uncomment the line below according to the target STM32G4 device used in your
|
||||||
|
application |
||||||
|
*/ |
||||||
|
|
||||||
|
#if !defined (STM32G431xx) && !defined (STM32G441xx) && !defined (STM32G471xx) && \ |
||||||
|
!defined (STM32G473xx) && !defined (STM32G474xx) && !defined (STM32G484xx) && \
|
||||||
|
!defined (STM32GBK1CB) && !defined (STM32G491xx) && !defined (STM32G4A1xx) && \
|
||||||
|
!defined (STM32G411xB) && !defined (STM32G411xC) && !defined (STM32G414xx) |
||||||
|
/* #define STM32G411xB */ /*!< STM32G411xB Devices */ |
||||||
|
/* #define STM32G411xC */ /*!< STM32G411xC Devices */ |
||||||
|
/* #define STM32G414xx */ /*!< STM32G414xx Devices */ |
||||||
|
/* #define STM32G431xx */ /*!< STM32G431xx Devices */ |
||||||
|
/* #define STM32G441xx */ /*!< STM32G441xx Devices */ |
||||||
|
/* #define STM32G471xx */ /*!< STM32G471xx Devices */ |
||||||
|
/* #define STM32G473xx */ /*!< STM32G473xx Devices */ |
||||||
|
/* #define STM32G483xx */ /*!< STM32G483xx Devices */ |
||||||
|
/* #define STM32G474xx */ /*!< STM32G474xx Devices */ |
||||||
|
/* #define STM32G484xx */ /*!< STM32G484xx Devices */ |
||||||
|
/* #define STM32G491xx */ /*!< STM32G491xx Devices */ |
||||||
|
/* #define STM32G4A1xx */ /*!< STM32G4A1xx Devices */ |
||||||
|
/* #define STM32GBK1CB */ /*!< STM32GBK1CB Devices */ |
||||||
|
#endif |
||||||
|
|
||||||
|
/* Tip: To avoid modifying this file each time you need to switch between these
|
||||||
|
devices, you can define the device in your toolchain compiler preprocessor. |
||||||
|
*/ |
||||||
|
#if !defined (USE_HAL_DRIVER) |
||||||
|
/**
|
||||||
|
* @brief Comment the line below if you will not use the peripherals drivers. |
||||||
|
In this case, these drivers will not be included and the application code will |
||||||
|
be based on direct access to peripherals registers |
||||||
|
*/ |
||||||
|
/*#define USE_HAL_DRIVER */ |
||||||
|
#endif /* USE_HAL_DRIVER */ |
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief CMSIS Device version number V1.2.5 |
||||||
|
*/ |
||||||
|
#define __STM32G4_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ |
||||||
|
#define __STM32G4_CMSIS_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */ |
||||||
|
#define __STM32G4_CMSIS_VERSION_SUB2 (0x05U) /*!< [15:8] sub2 version */ |
||||||
|
#define __STM32G4_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ |
||||||
|
#define __STM32G4_CMSIS_VERSION ((__STM32G4_CMSIS_VERSION_MAIN << 24)\ |
||||||
|
|(__STM32G4_CMSIS_VERSION_SUB1 << 16)\
|
||||||
|
|(__STM32G4_CMSIS_VERSION_SUB2 << 8 )\
|
||||||
|
|(__STM32G4_CMSIS_VERSION_RC)) |
||||||
|
|
||||||
|
/**
|
||||||
|
* @} |
||||||
|
*/ |
||||||
|
|
||||||
|
/** @addtogroup Device_Included
|
||||||
|
* @{ |
||||||
|
*/ |
||||||
|
|
||||||
|
#if defined(STM32G431xx) |
||||||
|
#include "stm32g431xx.h" |
||||||
|
#elif defined(STM32G441xx) |
||||||
|
#include "stm32g441xx.h" |
||||||
|
#elif defined(STM32G471xx) |
||||||
|
#include "stm32g471xx.h" |
||||||
|
#elif defined(STM32G473xx) |
||||||
|
#include "stm32g473xx.h" |
||||||
|
#elif defined(STM32G483xx) |
||||||
|
#include "stm32g483xx.h" |
||||||
|
#elif defined(STM32G474xx) |
||||||
|
#include "stm32g474xx.h" |
||||||
|
#elif defined(STM32G484xx) |
||||||
|
#include "stm32g484xx.h" |
||||||
|
#elif defined(STM32G491xx) |
||||||
|
#include "stm32g491xx.h" |
||||||
|
#elif defined(STM32G4A1xx) |
||||||
|
#include "stm32g4a1xx.h" |
||||||
|
#elif defined(STM32GBK1CB) |
||||||
|
#include "stm32gbk1cb.h" |
||||||
|
#elif defined(STM32G411xB) |
||||||
|
#include "stm32g411xb.h" |
||||||
|
#elif defined(STM32G411xC) |
||||||
|
#include "stm32g411xc.h" |
||||||
|
#elif defined(STM32G414xx) |
||||||
|
#include "stm32g414xx.h" |
||||||
|
#else |
||||||
|
#error "Please select first the target STM32G4xx device used in your application (in stm32g4xx.h file)" |
||||||
|
#endif |
||||||
|
|
||||||
|
/**
|
||||||
|
* @} |
||||||
|
*/ |
||||||
|
|
||||||
|
/** @addtogroup Exported_types
|
||||||
|
* @{ |
||||||
|
*/ |
||||||
|
typedef enum |
||||||
|
{ |
||||||
|
RESET = 0, |
||||||
|
SET = !RESET |
||||||
|
} FlagStatus, ITStatus; |
||||||
|
|
||||||
|
typedef enum |
||||||
|
{ |
||||||
|
DISABLE = 0, |
||||||
|
ENABLE = !DISABLE |
||||||
|
} FunctionalState; |
||||||
|
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) |
||||||
|
|
||||||
|
typedef enum |
||||||
|
{ |
||||||
|
SUCCESS = 0, |
||||||
|
ERROR = !SUCCESS |
||||||
|
} ErrorStatus; |
||||||
|
|
||||||
|
/**
|
||||||
|
* @} |
||||||
|
*/ |
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup Exported_macros
|
||||||
|
* @{ |
||||||
|
*/ |
||||||
|
#define SET_BIT(REG, BIT) ((REG) |= (BIT)) |
||||||
|
|
||||||
|
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) |
||||||
|
|
||||||
|
#define READ_BIT(REG, BIT) ((REG) & (BIT)) |
||||||
|
|
||||||
|
#define CLEAR_REG(REG) ((REG) = (0x0)) |
||||||
|
|
||||||
|
#define WRITE_REG(REG, VAL) ((REG) = (VAL)) |
||||||
|
|
||||||
|
#define READ_REG(REG) ((REG)) |
||||||
|
|
||||||
|
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) |
||||||
|
|
||||||
|
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) |
||||||
|
|
||||||
|
/* Use of CMSIS compiler intrinsics for register exclusive access */ |
||||||
|
/* Atomic 32-bit register access macro to set one or several bits */ |
||||||
|
#define ATOMIC_SET_BIT(REG, BIT) \ |
||||||
|
do { \
|
||||||
|
uint32_t val; \
|
||||||
|
do { \
|
||||||
|
val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \
|
||||||
|
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
|
||||||
|
} while(0) |
||||||
|
|
||||||
|
/* Atomic 32-bit register access macro to clear one or several bits */ |
||||||
|
#define ATOMIC_CLEAR_BIT(REG, BIT) \ |
||||||
|
do { \
|
||||||
|
uint32_t val; \
|
||||||
|
do { \
|
||||||
|
val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \
|
||||||
|
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
|
||||||
|
} while(0) |
||||||
|
|
||||||
|
/* Atomic 32-bit register access macro to clear and set one or several bits */ |
||||||
|
#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \ |
||||||
|
do { \
|
||||||
|
uint32_t val; \
|
||||||
|
do { \
|
||||||
|
val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
|
||||||
|
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
|
||||||
|
} while(0) |
||||||
|
|
||||||
|
/* Atomic 16-bit register access macro to set one or several bits */ |
||||||
|
#define ATOMIC_SETH_BIT(REG, BIT) \ |
||||||
|
do { \
|
||||||
|
uint16_t val; \
|
||||||
|
do { \
|
||||||
|
val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \
|
||||||
|
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
|
||||||
|
} while(0) |
||||||
|
|
||||||
|
/* Atomic 16-bit register access macro to clear one or several bits */ |
||||||
|
#define ATOMIC_CLEARH_BIT(REG, BIT) \ |
||||||
|
do { \
|
||||||
|
uint16_t val; \
|
||||||
|
do { \
|
||||||
|
val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \
|
||||||
|
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
|
||||||
|
} while(0) |
||||||
|
|
||||||
|
/* Atomic 16-bit register access macro to clear and set one or several bits */ |
||||||
|
#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \ |
||||||
|
do { \
|
||||||
|
uint16_t val; \
|
||||||
|
do { \
|
||||||
|
val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
|
||||||
|
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
|
||||||
|
} while(0) |
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @} |
||||||
|
*/ |
||||||
|
|
||||||
|
#if defined (USE_HAL_DRIVER) |
||||||
|
#include "stm32g4xx_hal.h" |
||||||
|
#endif /* USE_HAL_DRIVER */ |
||||||
|
|
||||||
|
#ifdef __cplusplus |
||||||
|
} |
||||||
|
#endif /* __cplusplus */ |
||||||
|
|
||||||
|
#endif /* __STM32G4xx_H */ |
||||||
|
/**
|
||||||
|
* @} |
||||||
|
*/ |
||||||
|
|
||||||
|
/**
|
||||||
|
* @} |
||||||
|
*/ |
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
@ -0,0 +1,285 @@ |
|||||||
|
/**
|
||||||
|
****************************************************************************** |
||||||
|
* @file system_stm32g4xx.c |
||||||
|
* @author MCD Application Team |
||||||
|
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File |
||||||
|
* |
||||||
|
* This file provides two functions and one global variable to be called from |
||||||
|
* user application: |
||||||
|
* - SystemInit(): This function is called at startup just after reset and |
||||||
|
* before branch to main program. This call is made inside |
||||||
|
* the "startup_stm32g4xx.s" file. |
||||||
|
* |
||||||
|
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used |
||||||
|
* by the user application to setup the SysTick |
||||||
|
* timer or configure other parameters. |
||||||
|
* |
||||||
|
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must |
||||||
|
* be called whenever the core clock is changed |
||||||
|
* during program execution. |
||||||
|
* |
||||||
|
* After each device reset the HSI (16 MHz) is used as system clock source. |
||||||
|
* Then SystemInit() function is called, in "startup_stm32g4xx.s" file, to |
||||||
|
* configure the system clock before to branch to main program. |
||||||
|
* |
||||||
|
* This file configures the system clock as follows: |
||||||
|
*============================================================================= |
||||||
|
*----------------------------------------------------------------------------- |
||||||
|
* System Clock source | HSI |
||||||
|
*----------------------------------------------------------------------------- |
||||||
|
* SYSCLK(Hz) | 16000000 |
||||||
|
*----------------------------------------------------------------------------- |
||||||
|
* HCLK(Hz) | 16000000 |
||||||
|
*----------------------------------------------------------------------------- |
||||||
|
* AHB Prescaler | 1 |
||||||
|
*----------------------------------------------------------------------------- |
||||||
|
* APB1 Prescaler | 1 |
||||||
|
*----------------------------------------------------------------------------- |
||||||
|
* APB2 Prescaler | 1 |
||||||
|
*----------------------------------------------------------------------------- |
||||||
|
* PLL_M | 1 |
||||||
|
*----------------------------------------------------------------------------- |
||||||
|
* PLL_N | 16 |
||||||
|
*----------------------------------------------------------------------------- |
||||||
|
* PLL_P | 7 |
||||||
|
*----------------------------------------------------------------------------- |
||||||
|
* PLL_Q | 2 |
||||||
|
*----------------------------------------------------------------------------- |
||||||
|
* PLL_R | 2 |
||||||
|
*----------------------------------------------------------------------------- |
||||||
|
* Require 48MHz for RNG | Disabled |
||||||
|
*----------------------------------------------------------------------------- |
||||||
|
*============================================================================= |
||||||
|
****************************************************************************** |
||||||
|
* @attention |
||||||
|
* |
||||||
|
* Copyright (c) 2019 STMicroelectronics. |
||||||
|
* All rights reserved. |
||||||
|
* |
||||||
|
* This software is licensed under terms that can be found in the LICENSE file |
||||||
|
* in the root directory of this software component. |
||||||
|
* If no LICENSE file comes with this software, it is provided AS-IS. |
||||||
|
* |
||||||
|
****************************************************************************** |
||||||
|
*/ |
||||||
|
|
||||||
|
/** @addtogroup CMSIS
|
||||||
|
* @{ |
||||||
|
*/ |
||||||
|
|
||||||
|
/** @addtogroup stm32g4xx_system
|
||||||
|
* @{ |
||||||
|
*/ |
||||||
|
|
||||||
|
/** @addtogroup STM32G4xx_System_Private_Includes
|
||||||
|
* @{ |
||||||
|
*/ |
||||||
|
|
||||||
|
#include "stm32g4xx.h" |
||||||
|
|
||||||
|
#if !defined (HSE_VALUE) |
||||||
|
#define HSE_VALUE 24000000U /*!< Value of the External oscillator in Hz */ |
||||||
|
#endif /* HSE_VALUE */ |
||||||
|
|
||||||
|
#if !defined (HSI_VALUE) |
||||||
|
#define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ |
||||||
|
#endif /* HSI_VALUE */ |
||||||
|
|
||||||
|
/**
|
||||||
|
* @} |
||||||
|
*/ |
||||||
|
|
||||||
|
/** @addtogroup STM32G4xx_System_Private_TypesDefinitions
|
||||||
|
* @{ |
||||||
|
*/ |
||||||
|
|
||||||
|
/**
|
||||||
|
* @} |
||||||
|
*/ |
||||||
|
|
||||||
|
/** @addtogroup STM32G4xx_System_Private_Defines
|
||||||
|
* @{ |
||||||
|
*/ |
||||||
|
|
||||||
|
/************************* Miscellaneous Configuration ************************/ |
||||||
|
/* Note: Following vector table addresses must be defined in line with linker
|
||||||
|
configuration. */ |
||||||
|
/*!< Uncomment the following line if you need to relocate the vector table
|
||||||
|
anywhere in Flash or Sram, else the vector table is kept at the automatic |
||||||
|
remap of boot address selected */ |
||||||
|
/* #define USER_VECT_TAB_ADDRESS */ |
||||||
|
|
||||||
|
#if defined(USER_VECT_TAB_ADDRESS) |
||||||
|
/*!< Uncomment the following line if you need to relocate your vector Table
|
||||||
|
in Sram else user remap will be done in Flash. */ |
||||||
|
/* #define VECT_TAB_SRAM */ |
||||||
|
#if defined(VECT_TAB_SRAM) |
||||||
|
#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field. |
||||||
|
This value must be a multiple of 0x200. */ |
||||||
|
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. |
||||||
|
This value must be a multiple of 0x200. */ |
||||||
|
#else |
||||||
|
#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. |
||||||
|
This value must be a multiple of 0x200. */ |
||||||
|
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. |
||||||
|
This value must be a multiple of 0x200. */ |
||||||
|
#endif /* VECT_TAB_SRAM */ |
||||||
|
#endif /* USER_VECT_TAB_ADDRESS */ |
||||||
|
/******************************************************************************/ |
||||||
|
/**
|
||||||
|
* @} |
||||||
|
*/ |
||||||
|
|
||||||
|
/** @addtogroup STM32G4xx_System_Private_Macros
|
||||||
|
* @{ |
||||||
|
*/ |
||||||
|
|
||||||
|
/**
|
||||||
|
* @} |
||||||
|
*/ |
||||||
|
|
||||||
|
/** @addtogroup STM32G4xx_System_Private_Variables
|
||||||
|
* @{ |
||||||
|
*/ |
||||||
|
/* The SystemCoreClock variable is updated in three ways:
|
||||||
|
1) by calling CMSIS function SystemCoreClockUpdate() |
||||||
|
2) by calling HAL API function HAL_RCC_GetHCLKFreq() |
||||||
|
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency |
||||||
|
Note: If you use this function to configure the system clock; then there |
||||||
|
is no need to call the 2 first functions listed above, since SystemCoreClock |
||||||
|
variable is updated automatically. |
||||||
|
*/ |
||||||
|
uint32_t SystemCoreClock = HSI_VALUE; |
||||||
|
|
||||||
|
const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; |
||||||
|
const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; |
||||||
|
|
||||||
|
/**
|
||||||
|
* @} |
||||||
|
*/ |
||||||
|
|
||||||
|
/** @addtogroup STM32G4xx_System_Private_FunctionPrototypes
|
||||||
|
* @{ |
||||||
|
*/ |
||||||
|
|
||||||
|
/**
|
||||||
|
* @} |
||||||
|
*/ |
||||||
|
|
||||||
|
/** @addtogroup STM32G4xx_System_Private_Functions
|
||||||
|
* @{ |
||||||
|
*/ |
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Setup the microcontroller system. |
||||||
|
* @param None |
||||||
|
* @retval None |
||||||
|
*/ |
||||||
|
|
||||||
|
void SystemInit(void) |
||||||
|
{ |
||||||
|
/* FPU settings ------------------------------------------------------------*/ |
||||||
|
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) |
||||||
|
SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ |
||||||
|
#endif |
||||||
|
|
||||||
|
/* Configure the Vector Table location add offset address ------------------*/ |
||||||
|
//#if defined(USER_VECT_TAB_ADDRESS)
|
||||||
|
SCB->VTOR = FLASH_BASE; /* Vector Table Relocation in Internal SRAM */ |
||||||
|
//#endif /* USER_VECT_TAB_ADDRESS */
|
||||||
|
} |
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Update SystemCoreClock variable according to Clock Register Values. |
||||||
|
* The SystemCoreClock variable contains the core clock (HCLK), it can |
||||||
|
* be used by the user application to setup the SysTick timer or configure |
||||||
|
* other parameters. |
||||||
|
* |
||||||
|
* @note Each time the core clock (HCLK) changes, this function must be called |
||||||
|
* to update SystemCoreClock variable value. Otherwise, any configuration |
||||||
|
* based on this variable will be incorrect. |
||||||
|
* |
||||||
|
* @note - The system frequency computed by this function is not the real |
||||||
|
* frequency in the chip. It is calculated based on the predefined |
||||||
|
* constant and the selected clock source: |
||||||
|
* |
||||||
|
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) |
||||||
|
* |
||||||
|
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) |
||||||
|
* |
||||||
|
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***) |
||||||
|
* or HSI_VALUE(*) multiplied/divided by the PLL factors. |
||||||
|
* |
||||||
|
* (**) HSI_VALUE is a constant defined in stm32g4xx_hal.h file (default value |
||||||
|
* 16 MHz) but the real value may vary depending on the variations |
||||||
|
* in voltage and temperature. |
||||||
|
* |
||||||
|
* (***) HSE_VALUE is a constant defined in stm32g4xx_hal.h file (default value |
||||||
|
* 24 MHz), user has to ensure that HSE_VALUE is same as the real |
||||||
|
* frequency of the crystal used. Otherwise, this function may |
||||||
|
* have wrong result. |
||||||
|
* |
||||||
|
* - The result of this function could be not correct when using fractional |
||||||
|
* value for HSE crystal. |
||||||
|
* |
||||||
|
* @param None |
||||||
|
* @retval None |
||||||
|
*/ |
||||||
|
void SystemCoreClockUpdate(void) |
||||||
|
{ |
||||||
|
uint32_t tmp, pllvco, pllr, pllsource, pllm; |
||||||
|
|
||||||
|
/* Get SYSCLK source -------------------------------------------------------*/ |
||||||
|
switch (RCC->CFGR & RCC_CFGR_SWS) |
||||||
|
{ |
||||||
|
case 0x04: /* HSI used as system clock source */ |
||||||
|
SystemCoreClock = HSI_VALUE; |
||||||
|
break; |
||||||
|
|
||||||
|
case 0x08: /* HSE used as system clock source */ |
||||||
|
SystemCoreClock = HSE_VALUE; |
||||||
|
break; |
||||||
|
|
||||||
|
case 0x0C: /* PLL used as system clock source */ |
||||||
|
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
|
||||||
|
SYSCLK = PLL_VCO / PLLR |
||||||
|
*/ |
||||||
|
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); |
||||||
|
pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1U ; |
||||||
|
if (pllsource == 0x02UL) /* HSI used as PLL clock source */ |
||||||
|
{ |
||||||
|
pllvco = (HSI_VALUE / pllm); |
||||||
|
} |
||||||
|
else /* HSE used as PLL clock source */ |
||||||
|
{ |
||||||
|
pllvco = (HSE_VALUE / pllm); |
||||||
|
} |
||||||
|
pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8); |
||||||
|
pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1U) * 2U; |
||||||
|
SystemCoreClock = pllvco/pllr; |
||||||
|
break; |
||||||
|
|
||||||
|
default: |
||||||
|
break; |
||||||
|
} |
||||||
|
/* Compute HCLK clock frequency --------------------------------------------*/ |
||||||
|
/* Get HCLK prescaler */ |
||||||
|
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; |
||||||
|
/* HCLK clock frequency */ |
||||||
|
SystemCoreClock >>= tmp; |
||||||
|
} |
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @} |
||||||
|
*/ |
||||||
|
|
||||||
|
/**
|
||||||
|
* @} |
||||||
|
*/ |
||||||
|
|
||||||
|
/**
|
||||||
|
* @} |
||||||
|
*/ |
||||||
|
|
||||||
|
|
||||||
@ -0,0 +1,104 @@ |
|||||||
|
/**
|
||||||
|
****************************************************************************** |
||||||
|
* @file system_stm32g4xx.h |
||||||
|
* @author MCD Application Team |
||||||
|
* @brief CMSIS Cortex-M4 Device System Source File for STM32G4xx devices. |
||||||
|
****************************************************************************** |
||||||
|
* @attention |
||||||
|
* |
||||||
|
* Copyright (c) 2019 STMicroelectronics. |
||||||
|
* All rights reserved. |
||||||
|
* |
||||||
|
* This software is licensed under terms that can be found in the LICENSE file |
||||||
|
* in the root directory of this software component. |
||||||
|
* If no LICENSE file comes with this software, it is provided AS-IS. |
||||||
|
* |
||||||
|
****************************************************************************** |
||||||
|
*/ |
||||||
|
|
||||||
|
/** @addtogroup CMSIS
|
||||||
|
* @{ |
||||||
|
*/ |
||||||
|
|
||||||
|
/** @addtogroup stm32g4xx_system
|
||||||
|
* @{ |
||||||
|
*/ |
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Define to prevent recursive inclusion |
||||||
|
*/ |
||||||
|
#ifndef __SYSTEM_STM32G4XX_H |
||||||
|
#define __SYSTEM_STM32G4XX_H |
||||||
|
|
||||||
|
#ifdef __cplusplus |
||||||
|
extern "C" { |
||||||
|
#endif |
||||||
|
|
||||||
|
/** @addtogroup STM32G4xx_System_Includes
|
||||||
|
* @{ |
||||||
|
*/ |
||||||
|
|
||||||
|
/**
|
||||||
|
* @} |
||||||
|
*/ |
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup STM32G4xx_System_Exported_Variables
|
||||||
|
* @{ |
||||||
|
*/ |
||||||
|
/* The SystemCoreClock variable is updated in three ways:
|
||||||
|
1) by calling CMSIS function SystemCoreClockUpdate() |
||||||
|
2) by calling HAL API function HAL_RCC_GetSysClockFreq() |
||||||
|
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency |
||||||
|
Note: If you use this function to configure the system clock; then there |
||||||
|
is no need to call the 2 first functions listed above, since SystemCoreClock |
||||||
|
variable is updated automatically. |
||||||
|
*/ |
||||||
|
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ |
||||||
|
|
||||||
|
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ |
||||||
|
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ |
||||||
|
|
||||||
|
/**
|
||||||
|
* @} |
||||||
|
*/ |
||||||
|
|
||||||
|
/** @addtogroup STM32G4xx_System_Exported_Constants
|
||||||
|
* @{ |
||||||
|
*/ |
||||||
|
|
||||||
|
/**
|
||||||
|
* @} |
||||||
|
*/ |
||||||
|
|
||||||
|
/** @addtogroup STM32G4xx_System_Exported_Macros
|
||||||
|
* @{ |
||||||
|
*/ |
||||||
|
|
||||||
|
/**
|
||||||
|
* @} |
||||||
|
*/ |
||||||
|
|
||||||
|
/** @addtogroup STM32G4xx_System_Exported_Functions
|
||||||
|
* @{ |
||||||
|
*/ |
||||||
|
|
||||||
|
extern void SystemInit(void); |
||||||
|
extern void SystemCoreClockUpdate(void); |
||||||
|
/**
|
||||||
|
* @} |
||||||
|
*/ |
||||||
|
|
||||||
|
#ifdef __cplusplus |
||||||
|
} |
||||||
|
#endif |
||||||
|
|
||||||
|
#endif /*__SYSTEM_STM32G4XX_H */ |
||||||
|
|
||||||
|
/**
|
||||||
|
* @} |
||||||
|
*/ |
||||||
|
|
||||||
|
/**
|
||||||
|
* @} |
||||||
|
*/ |
||||||
@ -0,0 +1,220 @@ |
|||||||
|
#define MAX_TASKS 2 |
||||||
|
#define TASK_STACK_SIZE 256 |
||||||
|
|
||||||
|
#include "stm32g431xx.h" |
||||||
|
#include "string.h" |
||||||
|
|
||||||
|
typedef unsigned int uint; |
||||||
|
|
||||||
|
volatile uint32_t sec = 0; |
||||||
|
int task_counter = 0; |
||||||
|
bool stop = false; |
||||||
|
|
||||||
|
struct Contexter |
||||||
|
{ |
||||||
|
uint R0; |
||||||
|
uint R1; |
||||||
|
uint R2; |
||||||
|
uint R3; |
||||||
|
uint R12; |
||||||
|
uint LR; // адрес возврата из ПП
|
||||||
|
uint PC; // счётки команд, на какой остановилась работа ПП
|
||||||
|
uint xPSR; // регистр состояния
|
||||||
|
}; |
||||||
|
|
||||||
|
struct Task |
||||||
|
{ |
||||||
|
uint sizeStack; |
||||||
|
uint *stack; |
||||||
|
int (*task)(); |
||||||
|
bool isActive; |
||||||
|
bool isFirstRun; |
||||||
|
uint returnError; |
||||||
|
}; |
||||||
|
|
||||||
|
Task task_list[MAX_TASKS]; |
||||||
|
|
||||||
|
Task myZeroTask; |
||||||
|
uint zeroStack[sizeof(Contexter)]; |
||||||
|
|
||||||
|
void PendSV_mainHandler(); |
||||||
|
|
||||||
|
extern "C" void SysTick_Handler() |
||||||
|
{ |
||||||
|
sec++; |
||||||
|
SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk; |
||||||
|
} |
||||||
|
|
||||||
|
extern "C" __task __stackless void PendSV_Handler(void) |
||||||
|
{ |
||||||
|
if (stop) |
||||||
|
{ |
||||||
|
asm volatile("MRS %0, PSP" : "=r"(myZeroTask.stack)); |
||||||
|
PendSV_mainHandler(); |
||||||
|
} |
||||||
|
|
||||||
|
asm volatile( |
||||||
|
"CMP R1, #1 \n" |
||||||
|
"IT EQ \n" |
||||||
|
"MSREQ PSP, R0 \n" // если первый раз запускается задача, загружаем указатель на стек из памяти
|
||||||
|
|
||||||
|
"MRS R0, PSP \n" |
||||||
|
"STMDB R0!, {R4-R11} \n" // Закидываем в стек r4-r11
|
||||||
|
"MSR PSP, R0 \n" :: |
||||||
|
|
||||||
|
"R0"(task_list[task_counter].stack), |
||||||
|
"R1"(task_list[task_counter].isFirstRun)); |
||||||
|
|
||||||
|
asm volatile("mov %0, R0" : "=r"(task_list[task_counter].stack)); |
||||||
|
|
||||||
|
task_list[task_counter].isFirstRun = false; |
||||||
|
|
||||||
|
PendSV_mainHandler(); |
||||||
|
} |
||||||
|
|
||||||
|
void __stackless PendSV_mainHandler() |
||||||
|
{ |
||||||
|
// Ищём следующую активную задачу для переключения на неё.
|
||||||
|
Task *myTask; |
||||||
|
|
||||||
|
int lastIndex = task_counter; |
||||||
|
|
||||||
|
do |
||||||
|
{ |
||||||
|
task_counter++; |
||||||
|
|
||||||
|
if (task_counter > MAX_TASKS - 1) |
||||||
|
task_counter = 0; |
||||||
|
|
||||||
|
myTask = &task_list[task_counter]; |
||||||
|
|
||||||
|
if (myTask->isActive) |
||||||
|
{ |
||||||
|
asm volatile("MSR PSP, %[psp]" ::[psp] "r"(myTask->stack)); |
||||||
|
|
||||||
|
if (!myTask->isFirstRun) |
||||||
|
asm volatile( |
||||||
|
"MRS r0, PSP \n" // Получаем PSP в r0
|
||||||
|
"LDMIA r0!, {r4-r11}\n" // Восстанавливаем r4-r11 из стека
|
||||||
|
"MSR PSP, r0 \n" // Обновляем PSP
|
||||||
|
); |
||||||
|
else |
||||||
|
myTask->isFirstRun = false; |
||||||
|
|
||||||
|
asm("mov LR, #0xFFFFFFFD"); |
||||||
|
|
||||||
|
stop = false; |
||||||
|
|
||||||
|
return; |
||||||
|
} |
||||||
|
|
||||||
|
} while (task_counter != lastIndex); |
||||||
|
|
||||||
|
// Если не нашли активную задачу переходим в заглущку
|
||||||
|
asm volatile("" ::"R0"(myZeroTask.stack)); |
||||||
|
|
||||||
|
asm volatile( |
||||||
|
"MSR PSP, R0 \n" // Обновляем PSP
|
||||||
|
); |
||||||
|
|
||||||
|
asm volatile("mov LR, #0xFFFFFFFD"); |
||||||
|
stop = true; |
||||||
|
} |
||||||
|
|
||||||
|
int func1(); |
||||||
|
int func2(); |
||||||
|
|
||||||
|
uint func1Stack[TASK_STACK_SIZE]; |
||||||
|
uint func2Stack[TASK_STACK_SIZE]; |
||||||
|
|
||||||
|
int a, b, c; |
||||||
|
|
||||||
|
int func1() |
||||||
|
{ |
||||||
|
int arr[10] = {0xab}; |
||||||
|
while (1) |
||||||
|
{ |
||||||
|
a++; |
||||||
|
// asm("mov R4, #0x12");
|
||||||
|
// asm("mov R5, #0x34");
|
||||||
|
// asm("mov R6, #0x56");
|
||||||
|
} |
||||||
|
} |
||||||
|
|
||||||
|
int func2() |
||||||
|
{ |
||||||
|
while (1) |
||||||
|
{ |
||||||
|
b++; |
||||||
|
// asm("mov R5, #0x79");
|
||||||
|
} |
||||||
|
} |
||||||
|
|
||||||
|
int mute() |
||||||
|
{ |
||||||
|
while (1) |
||||||
|
{ |
||||||
|
} |
||||||
|
} |
||||||
|
|
||||||
|
int newTask(int (*new_task)(), uint *stack, uint size) |
||||||
|
{ |
||||||
|
static int task_index = 0; |
||||||
|
|
||||||
|
Task &myTask = task_list[task_index]; |
||||||
|
|
||||||
|
myTask.stack = stack + size - sizeof(Contexter) / sizeof(uint); |
||||||
|
|
||||||
|
myTask.sizeStack = size; |
||||||
|
myTask.task = new_task; |
||||||
|
|
||||||
|
myTask.isActive = true; |
||||||
|
myTask.isFirstRun = true; |
||||||
|
|
||||||
|
Contexter *cx = (Contexter *)myTask.stack; |
||||||
|
|
||||||
|
cx->PC = (uint)new_task; |
||||||
|
cx->xPSR = 0x01000000; |
||||||
|
cx->LR = 0x0800029b; // LR - 0xFFFFFFFD (Возвращаемся в Thread режим, используем стек процесса PSP)
|
||||||
|
|
||||||
|
task_index++; |
||||||
|
|
||||||
|
return task_index; |
||||||
|
} |
||||||
|
|
||||||
|
void zeroTask(int (*new_task)(), uint *stack, uint size) |
||||||
|
{ |
||||||
|
Task &myTask = myZeroTask; |
||||||
|
|
||||||
|
myTask.stack = stack + (size - sizeof(Contexter)) / sizeof(uint); |
||||||
|
|
||||||
|
myTask.sizeStack = size; |
||||||
|
myTask.task = new_task; |
||||||
|
|
||||||
|
myTask.isActive = false; |
||||||
|
|
||||||
|
Contexter *cx = (Contexter *)myTask.stack; |
||||||
|
|
||||||
|
cx->PC = (uint)new_task; |
||||||
|
cx->xPSR = 0x01000000; |
||||||
|
cx->LR = 0x0800029b; |
||||||
|
} |
||||||
|
|
||||||
|
int main() |
||||||
|
{ |
||||||
|
int aaa[100]; |
||||||
|
|
||||||
|
aaa[99] = 0; |
||||||
|
|
||||||
|
SysTick_Config(SystemCoreClock); |
||||||
|
|
||||||
|
Task *muteVoid; |
||||||
|
zeroTask(mute, zeroStack, sizeof(Contexter)); |
||||||
|
|
||||||
|
newTask(func1, func1Stack, TASK_STACK_SIZE); |
||||||
|
newTask(func2, func2Stack, TASK_STACK_SIZE); |
||||||
|
|
||||||
|
while (true) |
||||||
|
{ |
||||||
|
} |
||||||
|
} |
||||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,7 @@ |
|||||||
|
<?xml version="1.0" encoding="UTF-8"?> |
||||||
|
<workspace> |
||||||
|
<project> |
||||||
|
<path>$WS_DIR$\stm32g4.ewp</path> |
||||||
|
</project> |
||||||
|
<batchBuild /> |
||||||
|
</workspace> |
||||||
Loading…
Reference in new issue